The management of the use of electric power within an electronic device has become extremely important. A device for electric power management as disclosed by Pardo/Webster in "Power Control Sequencer for Low Power and Battery Powered Applications," patent application Ser. No. 08/099,942, Jul. 30, 1993 generally:
1) determines when a function within an electronic device is idle, PA1 2) saves pertinent information relative to the state of that function, PA1 3) removes the power from those components that support the function, PA1 4) determines when the function is to be reactivated, PA1 5) reapplies power to the powered down components associated with the powered down function, and PA1 6) restores the function to a defined state. PA1 1) power is completely removed from functional circuits which are performing no useful function, and PA1 2) the PCS is intended for rapid, dynamic allocation of power within the electronic device. PA1 1) The power of an entire electronic device is managed by dividing the power supply circuit into power management sections. Because of physical design constraints, each section is usually defined to be an assembly or printed circuit board, or sections of a printed circuit board involving several integrated circuits. These power management sections can involve electronic device functions such as disk control, I/O control, memory management, etc. Power is applied and removed from each power management section by a "power gate," which is usually a electronically controlled power switch or a voltage regulator containing the electronic switch. Power management of more than one function on a single printed circuit board requires the designer to segment the printed circuit board's power plane into as many sections as there are functions to manage. This can lead to unwanted complexities in the routing of the printed circuit board and associated wiring, and usually precludes the power management of small functions involving one to a few integrated circuits. PA1 2) When power is applied to the printed circuit board's power plane, power filtering capacitors are usually present in the power circuit and are therefore charged. Removal of power in the power management process causes the capacitors to discharge, thus wasting the power used to charge them. This loss of power can be significant in applications where the "power-off" time is less than a few seconds. Loss of power to capacitive discharge/recharge decreases the efficiency and therefore the power savings available to an electronic device utilizing a PCS device which manages functions requiring rapid power cycling. PA1 3) Power managed on a power plane containing capacitance cannot be rapidly restored when compared to the nanosecond operation of today's electronics. Resistance and inductance in the routing back to the power supply coupled with the power plane capacitance constrains the power-up time of the power plane. This will limit the applicability of the PCS. PA1 4) Cycling of power on a printed circuit board or electronic device's power plane which contains discrete components, such as Tantalum capacitors, is not viewed as a reliable practice. PA1 5) Electrical isolation of PCS "powered-off" functions from "powered-on" functions is provided by a "buffer." As the complexity and number of the functions controlled increase, the complexity of the buffer also increases. The complexity of the buffer can become cumbersome to the designer. The buffer can also consume an inordinate amount of power which is contrary to the Power Control Sequencer concept. PA1 The first embodiment is seen as the long term solution to practical power management: a family of integrated circuits possessing many of the functions found in today's technology are created which contain the PMA functionality. New ASIC designs could directly incorporate the PMA. PA1 The second embodiment provides the PMA integrated into a integrated circuit separate from the functional circuit. The second embodiment allows an ease of design similar to the first embodiment, but this second embodiment can be used with existing technology. In the second embodiment, the new integrated circuit is "wired-up" between the integrated circuit to be power-managed and its external circuitry. PA1 The second embodiment allows existing integrated circuits to be mounted under-chip onto a socket containing a PMA integrated circuit providing power gate and I/O switch features. This combination of socket means and a PMA integrated circuit can be used with existing technology. PA1 a) adding one or more "power gate" functions to the integrated circuit substrate as depicted in FIGS. 2-4. The power gate(s), which serves the function of an electrically controllable power switch, is inserted between the power source input pad(s) and the integrated circuit's substrate power net(s) for that power type. The power gate(s) controls the distribution of power on the integrated circuit's substrate, PA1 b) adding one or more "I/O switch" functions to an integrated circuit substrate possessing a functional circuit as depicted in FIGS. 2-4. The I/O switch(s) is inserted between an I/0 pad and the integrated circuit substrate I/0 net for a given signal. The I/O switch serves as an electrically controllable signal switch between the two points. The I/O switch causes a low impedance connection between the I/0 pad and the I/O net when its control input terminal is asserted. The I/O switch causes a high impedance to exist between the I/0 pad and the I/O net when its control input terminal is deasserted. The I/O switch first protects the integrated circuit against externally induced latch-up, and second provides for the effective electrical isolation of the I/0 net from external circuitry, PA1 c) the state of the I/O switch and the power gate are controlled at their control input terminals by: PA1 1) a single electrical signal, or, PA1 2) a single, internally buffered electrical signal, or, PA1 3) two individually time sequenced electrical signals which are themselves driven from a single electrical signal.
The principal advantages of the Power Control Sequencer (PCS) for management of electrical power over other methods is:
Even small amounts of instantaneous power used consistently over a long period of time can added up to a significant amount of total power used. If a functional circuit is completely powered-down, it uses no power for the time it is "off," regardless of the length of that time. The functions considered by Pardo/Webster generally consists of a block of circuitry involving several to many integrated circuits or other electronic devices. Though possible, the management of many, single integrated circuits or other electronic devices on an individual basis was not generally envisioned by Pardo/Webster as practical.
A PCS is designed from several basic building blocks. These are the Controller, Power Gate, Initializer, Memory, Monitor, and Buffer. The design of a PCS is implemented by the circuit designer at the system, subsystem and assembly (printed circuit board) level using the basic PCS building blocks. In a typical PCS design, one or more "power gates" control the actual application of power to a given functional circuit, usually implemented over several to many integrated circuits. Power management is usually instantiated at the printed circuit board level. Although PCS devices can be adequately constructed using available technology, these devices can possess one or more undesirable characteristics which can be mitigated through the use of the present invention. The undesirable characteristics of a PCS device implemented using present technology are:
It would be desirable if present integrated circuit technology provided certain key power management features as built-in functions in order to obviate the currently defined PCS undesirable characteristics. Providing these features as built-in integrated circuit functions would also relieve the designer of having to understand and provide these functions when they are used in power management. Integrating these functions into individual integrated circuits will allow power management to extend down to the individual integrated circuit.
The present invention creates a "Power Management Apparatus (PMA)" for integrated circuits. The PMA is defined herein having several embodiments and several variations for each embodiment. The PMA combines several electronic "means" in unique ways to perform power management. The PMA draws from the PCS, recombining and reordering two of the PCS building blocks. A PMA incorporates the PCS function of "power gate means" and defines it specifically to be a "power switching means." A PMA also incorporates the PCS concept of "buffer means," but changes its function to the more suitable, and simpler "signal switching means." Instead of "buffering," the PMA uses "signal switching" to achieve the same effect: isolation of powered-on circuitry from powered-off circuitry. "Power switching means" and " signal switching means" are combined with and without functional circuits on integrated circuits which contain PMA. These new integrated circuits are further combined into chip and socket means to create new chip, and active circuit socket power management families.
The various embodiments of the PMA provide the designer with design tools from which power management can be more easily accomplished relative to the prior art. Using the PMA, power management can be accomplished at the individual integrated circuit level. Electronic devices designed using the PMA are simpler to generate, manufacture, and test. They would have a wider range of usefulness and would also be more reliable relative to a PCS designed into the same equipment. Most importantly, significant amounts of power can be saved in electronic devices which use the PMA relative to the current state-of-the-art. The inventors firmly believe that this novel device cannot be found anywhere in existing technology.